If the VCO requires higher tuning voltages, an active filter is typically required. The ADFHV can operate with charge-pump voltages as high as 30 V, thus avoiding the need for active filters in many cases. The low current drawn by the charge pump makes it look attractive to use a boost converter to generate the high charge-pump voltage from a lower supply voltage, but the switching-frequency ripple associated with this type of dc-to-dc converter could produce unwanted spurious tones at the output of the VCO.
High PLL spurs can potentially cause failure of a transmitter emission mask test or degrade sensitivity and out-of-band blocking in a receiver system. To help guide the specification of converter ripple, a comprehensive power supply rejection plot vs.
A ripple signal of At each frequency the spurious level was measured and the PSR calculated as the difference in dB between the —dBm input and the spurious output level.
The 0. The results are shown in Figure 7. The power supply rejection gets worse initially as the frequency increases within the PLL loop bandwidth. As the frequency approaches the PLL loop bandwidth, the ripple frequency gets attenuated in a similar manner to reference noise, and PSR improves. This plot shows that a boost converter with higher switching frequency—ideally greater than 1 MHz—is desirable to minimize switching spurs. Also, the PLL loop bandwidth should be minimized wherever possible.
With a switching speed of 1. Starting with the PLL spurious level requirements, one can work backward to determine the ripple level needed at the boost converter output. For example, if the PLL requires spurs less than —80 dBm, and the PSR is 50 dB, then the ripple power at the input to the charge pump supply needs to be less than —30 dBm, or 20 mV p-p. These levels of ripple voltage can easily be achieved with ripple filters, if sufficient decoupling capacitance is placed close to the charge pump supply pin.
For example, a nF decoupling capacitor provides more than 20 dB of ripple attenuation at 1. Care should be taken to use capacitors with the appropriate voltage rating; for example, if the boost converter generates an V supply, use capacitors with a V or higher rating.
Design of the boost converter and ripple filter is simplified using the ADPx Excel-based design tool. Figure 8 shows the user inputs for an illustrative 5-V in to V out design. To minimize voltage ripple at the output of the converter stage, the noise filter option was selected, and the V OUT ripple field was set to its minimum.
The current drawn by the high-voltage charge pump is 2 mA maximum, so an I OUT of 10 mA was typed in to provide margin. As a final experiment, the PSR of the high-voltage charge pump was compared to that of an active filter, the topology most commonly used today to generate high VCO tuning voltages. To make the measurement, an ac signal with an amplitude of 1 V p-p is injected into the charge pump supply V P of the ADFHV, using a passive loop filter—as in the measurement setup in Figure 6.
The same measurement is repeated with an active filter in place of the passive filter of equal bandwidth. The measured result is plotted in Figure the high-voltage charge pump has a dB to dB reduction in switching spur level when compared to the active filter. The improved spur levels with the high-voltage charge pump can be partially explained by the smaller loop filter attenuation seen by the active filter, where the injected ripple is after the first pole, in contrast to the passive filter, where the injected ripple is at the input.
Thus, it is advisable to choose a medium performance LDO that meets both the voltage and current requirements for this rail and apply sufficient decoupling close to all power pins; nF in parallel with 10 pF is usually sufficient.
The power-management requirements for the main PLL blocks were discussed, and specifications were derived for the VCO and charge pump supplies. With an understanding of the impact of power supply noise and ripple on PLL performance, designers can work back to derive specifications for power management blocks and achieve PLL designs with the best possible performance. ISBN Micronetics, Inc. Reprint: Microwave Journal.
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